The present invention relates to a delay circuit for a ring oscillator, and especially to a delay circuit for a ring oscillator which is capable of realizing CMOS integration, and is appropriate for application to a CMOS integrated PLL (Phase Lock Loop) in which a VCO (Voltage-controlled Oscillator) is realized in the ring oscillator.
In a ring oscillator circuit of a PLL circuit appropriate for a CMOS integrated circuit, a delay circuit for the ring oscillator is used. Generally, such a delay circuit for a ring oscillator has a circuit arrangement of a single input and single output type or a differential input and differential output type, and an amplification circuit of which gain is more than or equal to 1 is used in the delay circuit for the ring oscillator. In recent years, it is required for this delay circuit to be realized by a CMOS circuit having a circuit arrangement appropriate for circuit integration, and that a delay period of time between an input and an output of the circuit can be electronically adjusted for a temperature process variation.
A delay circuit for a ring oscillator for responding to such a requirement is disclosed in IEEE Journal of Solid State Circuits, Vol. No.SC-25, No.6, pp1385-1394, December 1990.
As shown in FIG. 8, the delay circuit for a ring oscillator disclosed in the aforementioned document includes PMOS transistors MP11 and MP12 which are always biased to a triode region by a reference voltage circuit 101, and thereby, an in-phase gain is suppressed to less than or equal to 1 and only a difference signal component generates oscillation. Furthermore, in this known technology, due to a voltage of a VBIAS terminal, a delay period of time, which is a period of time between an input voltage and an output voltage of the said delay circuit, is variable. In this manner, this known technology is formed as a delay circuit for a ring oscillator appropriate for CMOS circuit integration.
In case that the ring oscillator is constructed by using delay circuits, of which in-phase gain is more than or equal to 1, and as shown in FIG. 4, odd numbers of the delay circuits are used, a loop gain of an in-phase signal component of the ring oscillator becomes more than or equal to 1, and not only an oscillation output due to a differential signal component, but also an oscillation output due to an in-phase signal component are included in an output signal. In case that the ring oscillator is constructed by using delay circuits, of which in-phase gain is more than or equal to 1, and as shown in FIG. 5, even numbers of the delay circuits are used, similarly a loop gain of an in-phase signal component of the ring oscillator becomes to be more than or equal to 1, and in this case, a bistable circuit is formed and an output voltage of the ring oscillator finally becomes any one of voltage condition of a high voltage side VDD or a low voltage side VSS. Usually, since the ring oscillator using a differential input and differential output type delay circuit is designed so as to generate oscillation due to a differential signal component, a loop gain of an in-phase signal component is set to less than or equal to 1, and it is necessary to remove influence of unstabilization of an oscillation output due to the in-phase signal component.
Technology shown in FIG. 8 prevents an in-phase gain from becoming more than or equal to 1 by intentionally increasing conductance between the respective drains and sources of the PMOS transistors MP11 and MP12 which are loads. More particularly, gate voltages of the PMOS transistors MP11 and MP12 are set so that the PMOS transistors MP11 and MP12 which are loads always operate in a triode region. Generally, with regard to conductance between a drain and a source of a MOS transistor, compared with conductance between a drain and a source in a triode region, the conductance between the drain and the source in a saturation region is very small, and in case that the PMOS transistor MP11 and the PMOS transistor MP12 operate in the saturation region out of the triode region, an in-phase gain becomes more than or equal to 1. If a ring oscillator is constructed by such transistors, the ring oscillator having an odd stage arrangement shown in FIG. 4 can have condition in which oscillation occurs due to an in-phase signal component. Furthermore, the circuit of FIG. 8, which is a circuit having a differential input and a differential output, can realize a ring oscillator having an even stage arrangement shown in FIG. 5. However, in case that an in-phase gain of its delay circuit is more than or equal to 1, it becomes a bistable circuit and can have condition in which oscillation does not occur.
If it reaches such a condition, in order to always operate the PMOS transistors in the triode region, a reference voltage circuit for always supplying a constant voltage for a temperature variation and a process variation is necessary for gate voltages of these PMOS transistors, and as a result, a task that a chip area increases is derived.
It is desired that, without using the reference voltage circuit, a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1 are easily realized. Moreover, by realizing the differential gain of more than or equal to 1 and the in-phase gain of less than or equal to 1, it is desired to provide a delay circuit for a ring oscillator appropriate for CMOS integration.
The present invention is made to solve the above-mentioned problems.
Furthermore, the objective of the invention is to provide a delay circuit for a ring oscillator, which can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1, without using a reference voltage circuit.
Furthermore, the objective of the invention is to provide a delay circuit for a ring oscillator appropriate for CMOS integration by realizing the differential gain of more than or equal to 1 and the in-phase gain of less than or equal to 1.
Means for solving the objectives are described as follows. In technical items in the descriptions, which correspond to the claims, numerals, symbols and so forth are attached and described with parentheses ( ). Although the numerals, symbols and so forth clarify a coincidence or correspondence relation between the technical items corresponding to the claims and technical items in at least one embodiment out of a plurality of embodiments, they are not for showing that the technical items corresponding to the claims are restricted to the technical items in the embodiments.
A delay circuit for a ring oscillator in accordance with the present invention comprises a first electric potential line (VDD), a pair of output lines (2A, 2B), a pair of two first transistors (MP1, MP2) arranged between the first electric potential line (VDD) and the pair of output lines (2A, 2B), respectively, a second electric potential line (5), and a pair of two second transistors (MN1, MN2) arranged between the second electric potential line (5) and the pair of output lines (2A, 2B), respectively, and respective gates of the first transistors (MP1, MP2) are connected to the pair of output lines (2A, 2B), respectively, the two first transistors (MP1, MP2) are connected to each other center-symmetrically, and the two second transistors (MN1, MN2) are connected to each other center-symmetrically, and the delay circuit further comprises a third electric potential line (a ground line of FIG. 2, FIG. 3 or FIG. 7 or VDD of FIG. 6), and the pair of output lines (2A, 2B) are connected to the third electric potential line. (a ground line of FIG. 2, FIG. 3 or FIG. 7 or VDD of FIG. 6). Such a circuit can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.
It is preferable that, if the first transistors (MP1, MP2) are PMOS transistors, the second transistors (MN1, MN2) are NMOS transistors, and if the first transistors (MP1, MP2) are MMOS transistors, the second transistors are PMOS transistors.
Moreover, it is preferable to provide a pair of third transistors (MP3, MP4) arranged between the pair of output lines (2A, 2B) and the first electric potential line. In this case, gates of the first transistors (MP1, MP2) are center-symmetrically connected to gates of the third transistors (MP3, MP4), respectively.
Furthermore, it is also preferable to provide a pair of fourth transistors (MN3, MN4) arranged between the pair of output lines (2A, 2B) and the third electric potential line. In this case, gates of the fourth transistors (MN3, MN4) are connected to the output lines (2A, 2B), respectively.
Input voltages applied to gates of the two second transistors (MN1, MN2), respectively, are represented by V1 and V2, an in-phase input voltage with respect to the input voltages V1 and V2 is represented by VIQ, a differential input voltage included as a form of an input difference between the two inputs V1 and V2 is represented by xcex94VI, two output voltages which appear in the output lines (2A, 2B) are represented by Vo1 and Vo2, an in-phase output voltage which is commonly included in the output voltages Vo1 and Vo2 is represented by VOQ, a differential output voltage included as a form of an output difference between the output voltages Vo1 and Vo2 is included is represented by xcex94VO, transconductance of the first transistors (MP1, MP2) is represented by Gmp, transconductance of the second transistors (MN1, MN2) is represented by Gmn, transconductance between the output lines (2A, 2B) and the third electric potential line is represented by Gm.
If conductance as a design constant is set to Gds, an in-phase gain VOQ/VIQ of the said circuit is obtained by the following equation: VOQ/VIQ=xe2x88x92(Gmn*Gds/2)/{(Gmp+Gm)*(Gmn+Gds/2)}. If the design constant is defined so as to be Gmn greater than  greater than Gds/2, Gmn is eliminated in this equation, and an approximated equation: VOQ/VIQ=xe2x88x92(Gds/2)/(Gmp+Gm) is obtained. It is possible to further appropriately set the design constant Gds so that this in-phase gain becomes to be small enough. In this case, a differential gain xcex94VO/xcex94VI is expressed by the following equation: xcex94VO/xcex94VI=Gmn/(Gmpxe2x88x92Gm). Values of the parameters Gmn, Gmp and Gm are set so as to be Gmn greater than (Gmpxe2x88x92Gm). Moreover, the circuit comprises a forth electric potential line (VSS), and a bias transistor (MNB) arranged between the fourth electric potential line (VSS) and the second electric potential line, and conductance between a drain and a source of the bias transistor (MNB) coincides with the design constant Gds. Such a circuit surely realizes a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.